This invention pertains to an output stage, and more particularly to an output stage and method for preventing offset voltage error and improving output stability and performance.
It is known in the prior art to provide some degree of output stage control for amplifier outputs. However, prior art amplifier output stages have several limiting features which affect the amplification of the amplifier input signal and fail to provide adequate control of the amplifier output.
FIG. 1 depicts an example of a prior art amplifier 120 with an output stage 122. One of the problems with prior art amplifier output stages is that they cause an excessively large reflection current (xcex94I) to be reflected back into amplifier 120. The current reflection xcex94I will be reflected back through transconductance amplifier 120 and produce a systematic input offset error voltage (VOS) which can have significant effects on the performance of amplifier 120. The resulting offset error voltage VOS is equivalent to the reflection current xcex94I divided by the amplifier transconductance (gm), VOS=xcex94I/gm. Therefore, any increase in xcex94I will result in an unwanted increase in offset error voltage VOS.
In the prior art amplifier output stage 122, current Io provides the driving current to the base of a source NPN transistor Q3 which in turn controls the current flow through transistor Q3 and thus output voltage Vout. Because the base current IB of a transistor provides control for the collector current IC through the known beta factor relationship of IC=IB*xcex2, IB3 provides control for the collector current IC3 of transistor Q3 and thus the output voltage Vout. Therefore, to achieve a sufficiently large output voltage, Vout, through transistor Q3, base current IB3 of transistor Q3 must be sufficiently large to drive IC3. To achieve a sufficiently large IB3, the base current of transistor Q1 (IB1) must be sufficiently large (again, IC=IB*xcex2) to generate a sufficiently large Io current to drive transistor Q3.
This large base current IB1 causes a significant increase in the current at node N1. This increase at node N1 results in an increase in reflection current xcex94I. The resulting increased xcex94I is reflected back through transconductance amplifier 120 resulting in an increased offset error voltage VOS which in turn affects the overall amplifier output voltage Vout, depending on the closed-loop gain.
A similar analysis can be made with regard to driving transistor Q2 which drives sink output transistor Q4. To achieve a sufficiently large output current through transistor Q4, a base current (IB4) of transistor Q4 must be sufficiently large to produce a sufficiently large collector current (IC4) for transistor Q4. Therefore, Io through driving transistor Q2 must be sufficient to drive sink output transistor Q4. This requires an increase in base current (IB2) for transistor Q2 which in turn affects the current at node N1.
The prior art output stage 122 further affects the overall amplifier output voltage Vout because of the needed implementation of Q1 as a fast PNP transistor. To achieve a desired bandwidth and efficiency, Q1 needs to be a fast transistor. Therefore, the Q1 transistor is implemented with a vertical PNP configuration to improve response time. However, fast, vertical PNP transistors have a reduced xcex2, which in turn reduces the driving current Io. Thus, to maintain Io at a sufficiently large level to drive source transistor Q3, IB1 must be further increased. The further increase to IB1 causes an increase in the current at node N1, resulting in an increase in reflection current xcex94I and thus an increase in offset error voltage VOS.
What is needed is an amplifier output stage which provides a sufficiently large driving current to the base of a source transistor without adversely increasing the reflection current xcex94I. What is further needed is an output stage which will significantly reduce or eliminate any reflection current xcex94I, where xcex94I is due to a mismatch of beta factors of NPN transistors (xcex2npn) and PNP transistors (xcex2pnp).
The present invention provides for an output stage which couples with an input stage and is configured to limit a reflection current which is reflected back through the input stage producing an offset error input voltage affecting the performance of the input stage. The present output stage limits the reflection current by compensating for at least one bias current at the input stage output. The output stage further reduces a quiescent current needed to maintain the output stage in an active state without adversely affecting the output voltage supplied to the load. The output stage includes a first and second current driving stage, a first and second current compensation circuit and an output circuit. The first and second current driving stages couple with both the input stage and the output circuit. The first current driving stage is configured to generate a first driving current to drive the output circuit, wherein the first driving current is proportional to a first bias current based on an output from the input stage. The second driving stage is configured to generate a second driving current to also drive the output circuit, wherein the second driving current is proportional to a second bias current based on the output of the input stage. To limit reflection current back into the input stage, the first current compensation circuit couples with the first driving stage and the input stage, and is configured to compensate for the first bias current. To further limit the reflection current back into the input stage, the second current compensation circuit couples with the second driving stage and the input stage, and is configured to compensate for the second bias current.
In one embodiment, the first current driving stage further includes a first current multiplier coupled with the output circuit, and is configured to drive the output circuit at a sufficient level while limiting the first bias current. The second current driving stage further includes a second current multiplier coupled with the output circuit, and is configured to drive the output circuit at a defined level while limiting the second bias current. The first current compensation circuit includes a first current mirror coupled with the first current driving stage to compensate for the first bias current and the second current compensation circuit includes a second current mirror coupled with the second current driving stage to compensate for the first bias current. The output stage further includes a clamping stage coupled with the input stage and the output circuit, and a feedforward path coupled between the input stage and the output circuit. The clamping stage is configured to maintain the output level of the output stage to be approximately equal to the input stage output, while the feedforward path is configured to stabilize the output stage output at high frequencies.
In one embodiment, the first current compensation circuit further includes a PNP sink transistor coupled with the first current driving stage to sink a first driving stage total collector current from the first current driving stage. The PNP sink transistor is configured to define a first compensation current to compensate for the first bias current wherein the first bias current is about equal to a total collector current of the first current driving stage divided by a PNP beta factor. Further, the second current compensation circuit includes an NPN source transistor coupled with the second current driving stage to supply a second driving stage total collector current from the second current driving stage. The NPN source transistor is configured to define a second compensation current to compensate for the second bias current wherein the second bias current is about equal to a total collector current of the second current driving stage divided by an NPN beta factor.
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